In recent years, there has been an interest in increasing the integration density of integrated circuits (ICs). This interest is driven by the requisite for ICs having low-power dissipation, higher performance, increased circuit functionality and reduced fabrication cost. Power dissipation may be reduced by lower operation voltages that may require the geometry of the IC to be scaled down to achieve a desired performance. As geometries scale down, conductor length and parasitic capacitance decrease resulting in a decrease in signal propagation time. Furthermore, there are certain economic benefits of reduced processing cost resulting in the formation of a greater number of circuits on a single wafer or chip. However, as active devices are scaled to smaller dimensions, the device voltage must also be scaled down in order to provide a device that is reliable. Therefore, scalability of devices is constrained by the competing consideration of device performance and reliability.
In some circumstances, scaling of other types of devices to smaller sizes may have a deleterious effect on performance, particularly when the capacitance coupling effects are relied upon for device operability. FETs, which typically rely on alteration of conduction characteristics of a device channel in a semiconductor body by a capacitively coupled electrical field, when scaled to extremely small lateral dimensions, do not exhibit scalability of drive voltages, particularly in conduction threshold voltage (Vt). In fact, it is sometimes quite difficult to avoid increasing the Vt for a given off-current because the sub-threshold slope degrades with higher doping concentrations; higher doping concentration is typically required to reduce short channel effects because of the limits on the minimum thickness of the gate dielectric material. Additionally, reduced size limits the gate voltage (Vg) that can be applied to the device without breakdown and the lack of scalability in Vt reduces the available overdrive voltage (Vg−Vt) with a consequent reduction of available on-current of the device. Hence, existing bulk complementary metal oxide semiconductor (CMOS) technologies cannot be extended into very low operating voltages (on the order of less than 1.5 V).
To avoid the above-mentioned limitation with existing CMOS technologies, very-low temperature operation and silicon-on-insulator (SOI) structures have been proposed in an attempt to reduce Vt. However, the use of low operation temperatures in CMOS devices imposes server limitations on such devices including, for example, the possibility of using the same as a portable device, as well as the increased cost of operating such a CMOS device. Also, packaging reliability may arise with using low operation temperature CMOS devices. SOI devices, on the other hand, suffer from floating body effects and the cost of manufacturing the SOI structure itself.
In addition to the above proposals, a very narrow channel MOSFET structure has been developed in order to improve sub-threshold slope and high conduction current; See, for example, IBM Technical Bull. Vol. 34, No. 12, pp. 101–102 (May 1992) entitled “Corner Enhanced Field-Effect Transistor”. In that prior art disclosure, corner conduction effects, which are generally considered to be parasitic at unavoidable edges of the channel, were exploited such that the corners dominate over the conduction in the remaining of the channel. This principal was extended, as described in the IBM Technical Bull. to a so-called multi-mesa structure by repeated conformal deposition and anisotropic etching of alternating layers of nitride and polysilicon which serve to fill the area between shallow trench isolation (STI) regions and form a plurality of narrow channels extending from the source to the drain of the transistor.
The fabrication of multi-mesa structures using the above processing steps of repeated deposition and etching is extremely expensive and, in some circumstances, compromises manufacturing yields. Further, corner dominated conduction implies high-levels of mesa doping to suppress conduction in other areas besides the corner regions. The prior art multi-mesa device also suffers from disproportionately high gate/input capacitance since significant portions of the area of the gate do not correspond to regions which significantly contribute to the conduction of the device.
Another approach to forming a similar multi-mesa device is disclosed, for example, in IBM Technology Bull. Vol. 34, No. 10A (March 1992), pp. 472–473. In this disclosure, slits are etched into a channel region formed in an SOI or bulk structure such that each slit essentially forms two back-to-back FETs, with the thickness of the channel layers defining the channel width. In this prior art method, the above problems with SOI structures are not obviated. Moreover, the slit and intervening channel size of the prior art structure is limited by minimum feature sizes obtainable with current lithography; limiting the minimum “footprint” in which the transistor can occupy.
U.S. Pat. No. 5,675,164 to Brunner, et al. provide a multi-mesa structure having sub-lithographic mesa widths and periodicity. The multi-mesa structure disclosed in Brunner, et al. is formed using a subtractive gate etching process which includes the steps of: exposing a pattern of lines on a photoresist, said pattern of lines having a pitch that is less than one-half micron; etching grooves of sub-lithographic width forming a grooved surface including mesa structures; forming an oxide on said grooved surface; and applying a gate electrode over the oxide.
One drawback of subtractive gate etching processes such as disclosed in the Brunner, et al. patent is that gate conductor stringers remain between the mesas. Furthermore, prior art subtractive gate etching processes do not permit channel doping in each mesa to be spaced away from the source/drain junctions edges, therefore, the prior art mesa structures have a relatively high drain electrical field associated therewith which serves to decrease the hot-carrier reliability and to increase the body charging effects of the device.
In addition to the above drawbacks with prior art methods of fabricating multi-mesa structures, prior art methods also have the following problems associated therewith: (i) The aspect ratio of the mesas (grooves) is limited because of the difficulty of delivering the same level of dopant using ion implantation throughout the depth of the source or drain, each of which is a single block of silicon and exposed only on the top for any doping method. (ii) The current drive distribution is highly non-uniform due to the non-uniform vertical source/drain doping profiles; and (iii) The use of a spacer for gate extension formation plugs up the mesas that need to be selectively etched out while protecting gate spacers.
According, there is a need for providing a new and improved method of fabricating multi-mesa FET structures that have improved electrical characteristics such as an improved sub-threshold slope, negligible back bias sensitivity, a high immunity to drain induced barrier lowering (DIBL), and a high current drive.